SOA-MZI based optical AND gate design on optisytem-7

[SUSHMITA JAIN]

Sir,
Here i am unable to understand the logic of AND gate design. here author chose (A+B) in upper arm and B in lower arm. For the same design I got output 0010. for input (A= 0011) and input (B=0101). I got 1 at input A = 1 & B=0. but output should be 1 for input A =1 & input B=1.please help me for designing this gate. here i am attaching AND gate design on optisystem-7

• This topic was modified 3 years, 1 month ago by SUSHMITA JAIN.

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[Ahmad Atieh]

Dear Sushmita,
As discussed by emails, there are many issues with your setup.
1. You are using wrong wavelengths in the MUX components.
2. You are using different wavelength at input of the idea Mux. Why?
3. Number of leading and trailing zeros should be 0 in PRBS.
4. You can setup the sequence length to 4 bits and view easier the output.

It would be easier to provide a published reference that you’d like to reproduce its results.
Regards,
Ahmad

[Author]

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