how to design 1 bit delay ?

[Saran Bala]

I want to design D flip flop as like as in journal paper…but i dont know how to implement 1 bit delay …….also i have another one doubt…in this design they are using two input plane…but at a time one input plane will be enabled…2nd i/p plane was assumed as feedback of previous output…i dnt know how its working???…can anyone explain me…i,’m eagerly waiting for your valuable points..

Attachments:

1. 

   D-ff.jpg
   

[Saran Bala]

simulation diagram for D FF

Attachments:

1. 

   D.jpg
   

[Saran Bala]

can anyone clarify my doubt plz…

Attachments:

1. kumar2015.pdf

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