cannot connect wire

[Dr. Dhiman Kakati]

I am unable to connect the output port of modulator to the input port of coherent receiver in the attached .osd file. I am facing this problem when I create a subsystem otherwise its working fine. Please help.

[alistu]

Hi Dhiman, Your osd file is not attached.

[Dr. Dhiman Kakati]

Dear alistu sorry for my mistake.. Plz find the attached file.

with regards

Attachments:

1. NRZ-QPSK.osd

[alistu]

Thanks for attaching. I took a look at your file and found that only the output and input of two subsystems (the ones you have most probably referred to in your post) are not connected, so I simply connected them together without any problem and since the BER analyzer is showing results, I assume the problem is solved. Please see if it is so.

Regards

Attachments:

1. NRZ-QPSK-modified.osd

[Dr. Dhiman Kakati]

Dear alistu, The .osd file you have attached shows error(Attached) when I try to open it. Presently i am using optisystem 30 days trial version.

with Regards

Attachments:

1. 

   open.jpg
   

[alistu]

I really don’t know about the error. I could easily make the connection and the BER I get is attached. Are you using version 13.0.3?

I have also encountered more or less the same problem regarding wire connection many times in my simulations with many subsystems, but when I close the file and open it again, I am able to make the connection.

Attachments:

1. 

   ber-connect.jpg
   

[Dr. Dhiman Kakati]

Thanks for the reply,
I am using optisystem version Product Version: 13,0,3, 474, Still in my case i cant connect after restarting the program also.

[alistu]

What about copying your whole system layout into a new osd file and then set the layout parameters like the ones in your original osd file? I remember once having to implement the system again in a new osd file (I had made the connection, but after I opened a subsystem and made some changes in it, the connection was not there and when I wanted to connect again, the “already connected” error was displayed below the layout. I guess I made a mistake by saving the file then. I am not sure though). But that’s all I can say. I hope it works, or you get technical help from Optiwave.

[Dr. Dhiman Kakati]

copying all the components to a new file it works, Thanks

[alistu]

You’re welcome.

[Dr. Dhiman Kakati]

I am still getting the same problem of connecting the wires, Then what I do is to restart my laptop or copy paste the design to anew layout. but why this is happening I do not know, I downloaded many a times the latest version still the same problem exits. though I have the solution to this (I mentioned in the above line) but doing so again and again leads to frustration. this problem occurs in the case where I make a subsystem as I mentioned in previous comments. So I want to know the cause of this problem and how to get rid of it.

Regards

[alistu]

It bothers me a lot too Dhiman. However, there is something you can do to avoid restarting computer and copying implementation to a new layout. Whenever you realize you cannot connect a wire due to the fact that “the port is already connected” while you see no connection, simply save your progress, close the program and reopen it. You will see the wire is connected. Please let me know if this also works for you.

Regards

[Dr. Dhiman Kakati]

Closing and reopening the program does not work for me, only restarting pc or coping the complete design to a new layout works. I am expecting here a comment from the optisystem designers. this issue is an old one but still getting no response for the same. I agree to you what you have mentioned, only the developers will know exact reason for this.

Regards..

[Damian Marek]

Dhiman, I have confirmed that this is a bug and we will get it fixed in the coming version of OptiSystem.

Apologies for the inconvenience!

[Dr. Dhiman Kakati]

Thank you Damian for the response from optiwave side. Can you tell me when next version of optisystem will be released.

Regards

[Author]

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