SOA-MZI based optical AND gate design on optisytem-7 - Optiwave

Free Evaluation

This topic has 1 reply, 2 voices, and was last updated 3 years, 8 months ago by Ahmad Atieh.

Viewing 1 reply thread

Author

Posts
- March 2, 2021 at 5:52 am #69007
  SUSHMITA JAIN
  Participant
  Sir,
  Here i am unable to understand the logic of AND gate design. here author chose (A+B) in upper arm and B in lower arm. For the same design I got output 0010. for input (A= 0011) and input (B=0101). I got 1 at input A = 1 & B=0. but output should be 1 for input A =1 & input B=1.please help me for designing this gate. here i am attaching AND gate design on optisystem-7
  - This topic was modified 3 years, 9 months ago by SUSHMITA JAIN.
- March 9, 2021 at 7:40 am #69039
  
  Ahmad Atieh
  Moderator
  
  Dear Sushmita,
  As discussed by emails, there are many issues with your setup.
  1. You are using wrong wavelengths in the MUX components.
  2. You are using different wavelength at input of the idea Mux. Why?
  3. Number of leading and trailing zeros should be 0 in PRBS.
  4. You can setup the sequence length to 4 bits and view easier the output.
  
  It would be easier to provide a published reference that you’d like to reproduce its results.
  Regards,
  Ahmad
Author

Posts

Viewing 1 reply thread

You must be logged in to reply to this topic.