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    • #33651
      Jamal
      Participant

      Hi all,
      I am testing a 10 bit ADC of 16GHz sampling rate.
      The ideal SNR for ADC = 6.02(N) + 1.76 and for 10 bits it would give 61.96dB.
      Due to fft, processing gain pushes down the noise floor by 10log(M/2) where M is the number of samples, and for 4096 samples, processing gain is 33.1.
      So following the image attached, the noise floor must be SNR + Processing gain = 61.98+33.1 = 95 db but through simulations, it is not so. The noise floor comes around 102db as shown in the image.
      Can anyone explain why is this so ?

    • #33653
      Jamal
      Participant

      Simulated Result

    • #33686
      Jamal
      Participant

      PFA

    • #33772
      Ranjeet Kumar
      Participant

      Hi Jamal,
      Could you please upload the osd file of the design.
      Then i will try to sort out the problem if i could.
      i am unable to understand properly the issues related to your designs.
      As you have 16GHz sampling rate, but at the same time you have taken M is the number of samples, and for 4096 samples for calculation of :
      Due to fft, processing gain pushes down the noise floor by 10log(M/2) where M is the number of samples, and for 4096 samples, processing gain is 33.1.
      Seeking for your response.

    • #33997
      Jamal
      Participant

      Hi Ranjeet and Rather

      Please find the attached osd and .m files

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