Fiber nonlinearities and residual dispersion

[siva rama krishna]

Hi,

I an trying to do example Enginnering the fiber nonlinearities and dispersion single channel.osd

I implemented WDM layout as given in link

Engineering the Fiber Nonlinearities and Dispersion

1) I an getting high BER(2*10^-6) for zero dispersion value for iterations input power as 0dBm,10dBm,13dBm.But this should not be get.

2) I am trying to implement the paper (Dependence of self-phase modulation impairments on residual dispersion in 10 Gb/s based terrestrial transmission using standard fiber”) i am stuck at fig 2
How to get penalty @10^-10 BER vs Channel power (Pin)

This is urgent to implement

Please anyone assistme in this paper

Thanks and Regards
Siva Rama Krishna

[Alessandro Festa]

Hi Siva, dispersion is not the only parameter you should look at to have good BER. What are received signal and OSNR?

[Ravil]

Hi, did you consider fiber nonlinearities and noise (primarily from EDFA) beside dispersion? They affect your OSNR as well.

[siva rama krishna]

Signal power:-3.04,7,8.97dBm
OSNR: 96.8,106.64,107.61 dBm for input power as 0,10,13dBm respectively

[Alessandro Festa]

The numbers look strange…anyway >7 dBm is too much for a receiver, try to put an attenuator to receive < -5dBm

[Damian Marek]

Hi Siva,

Attaching your project file makes it much easier to troubleshoot!

Regards

[siva rama krishna]

Hi Damian

Please find the attached project.
Please provide the necessary assistance to complete this project.

[Damian Marek]

I think you only need to increase the sequence length of your bit stream. I put it to 512 bits and got a BER of ~5e-10. You can try an even larger sequence length to get a more accurate simulation.

[Ravil]

Hi Siva, according to my observation short bit sequences (less then 512 bits) gave me unexpected/random results (esp. for schemes with disp and nonlon.). In general, I’d recommend you to use 1024 or more bits.

[siva rama krishna]

Thanks Damian Marek,Ravil for your valuable feedback.

One more question
How to plot power penalty vs input power as shown in attached paper above?
Hot to get power penalty using optisystem components?

Thanks in advance
Siva Rama Krishna

[Damian Marek]

You can follow the link here to a forum post:

System Power Penalty and Link Margin

There is also a tutorial at:

System Design – Power Budget

[Author]

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