Hi Jamal,
Could you please upload the osd file of the design.
Then i will try to sort out the problem if i could.
i am unable to understand properly the issues related to your designs.
As you have 16GHz sampling rate, but at the same time you have taken M is the number of samples, and for 4096 samples for calculation of :
Due to fft, processing gain pushes down the noise floor by 10log(M/2) where M is the number of samples, and for 4096 samples, processing gain is 33.1.
Seeking for your response.